1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same.
Priority is claimed on Japanese Patent Application No. 2009-288045, Dec. 18, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, the miniaturization of dynamic random access memory (DRAM) cells has necessitated a reduction in gate length of an access transistor (hereinafter, referred to as a “cell transistor”) of a cell array. However, as the gate length of the cell transistor decreases, a short channel effect of the cell transistor increases. Thus, the threshold voltage Vt of the cell transistor is reduced due to an increase in subthreshold current. Also, when the concentration of a substrate is increased to suppress a drop in threshold voltage Vt, junction leakage increases. As a result, deterioration of refresh characteristics of a DRAM may occur.
Japanese Unexamined Patent Application, First Publications, Nos. JP-A-2006-339476 and JP-A-2007-081095 disclose a trench-gate transistor (also referred to as a “recess channel transistor”) in which a gate electrode is buried in a trench formed in a silicon substrate. Since it is possible to sufficiently ensure an effective channel length, which is a gate length, of the trench-gate transistor, even a fine DRAM with a minimum processing dimension of about 60 nm or less may be realized.